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Update Encoding DP Register for readability

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sBubshait 2024-06-13 18:40:17 +01:00
parent 873c0b60cb
commit cea9590621
1 changed files with 30 additions and 48 deletions
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76
src/twopassassembly.c
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@ -102,56 +102,38 @@ word dpi(a64inst_instruction cI) {
} }
word dpr(a64inst_instruction cI) { word dpr(a64inst_instruction cI) {
word out = 0; word wrd = 0;
a64inst_DPRegisterData data = cI.data.DPRegisterData; a64inst_DPRegisterData data = cI.data.DPRegisterData;
// sf setBits(&wrd, 31, 32, data.regType); // sf
int sf = data.regType; setBits(&wrd, 29, 31, data.processOp); // opc
// bits 27-25 setBits(&wrd, 28, 28, data.DPROpType); // M
out += 5 * (1 << 25); setBits(&wrd, 25 ,28, 0x5);
int m = data.DPROpType; setBits(&wrd, 16, 21, data.src2); // src2
int opc = 0; setBits(&wrd, 5, 10, data.src1); // src1
int opr = 0; setBits(&wrd, 0, 5, data.dest); // src2
int rm = 0;
int operand = 0; if (data.DPROpType == a64inst_DPR_MULTIPLY) {
int rn = 0; setBits(&wrd, 21, 31, 0xD8);
int rd = 0; setBits(&wrd, 15, 16, data.processOpData.multiplydata.negProd);
// multiply setBits(&wrd, 10, 15, data.processOpData.multiplydata.summand);
if (m == 1) {
// opc = 0; } else {
opr = 8; // Arithmetic Logic Instruction
if (data.processOpData.multiplydata.negProd) { setBits(&wrd, 22, 24, data.processOpData.arithmLogicData.shiftType);
operand += 32; setBits(&wrd, 10, 16, data.processOpData.arithmLogicData.shiftAmount);
if (data.processOpData.arithmLogicData.type == a64inst_DPR_ARITHM) {
// Arithmetic
setBits(&wrd, 24, 25, 0x1); // bit 24
} else {
setBits(&wrd, 21, 22, data.processOpData.arithmLogicData.negShiftedSrc2);
} }
operand += data.processOpData.multiplydata.summand;
} }
// arithmetic and logical
else { return wrd;
// shift
opr += 2 * data.processOpData.arithmLogicData.shiftType;
// arithmetic
if (data.processOpData.arithmLogicData.type == 1) {
opr += 8;
}
// logical
else {
if (data.processOpData.arithmLogicData.negShiftedSrc2) {
opr += 1;
}
}
operand += data.processOpData.arithmLogicData.shiftAmount;
}
rm += data.src1;
rn += data.src2;
rd += data.dest;
out += sf * (1 << 31);
out += opc * (1 << 29);
out += m * (1 << 28);
out += opr * (1 << 21);
out += rm * (1 << 16);
out += operand * 1024;
out += rn * 32;
out += rd;
return out;
} }
word sts(a64inst_instruction cI) { word sts(a64inst_instruction cI) {