diff --git a/src/twopassassembly.c b/src/twopassassembly.c
index e9fcf2e..0a03c7e 100644
--- a/src/twopassassembly.c
+++ b/src/twopassassembly.c
@@ -102,56 +102,38 @@ word dpi(a64inst_instruction cI) {
 }
 
 word dpr(a64inst_instruction cI) {
-    word out = 0;
+    word wrd = 0;
+
     a64inst_DPRegisterData data = cI.data.DPRegisterData;
-    // sf
-    int sf = data.regType;
-    // bits 27-25
-    out += 5 * (1 << 25);
-    int m = data.DPROpType;
-    int opc = 0;
-    int opr = 0;
-    int rm = 0;
-    int operand = 0;
-    int rn = 0;
-    int rd = 0;
-    // multiply
-    if (m == 1) {
-        // opc = 0;
-        opr = 8;
-        if (data.processOpData.multiplydata.negProd) {
-            operand += 32;
-        }
-        operand += data.processOpData.multiplydata.summand;
+    setBits(&wrd, 31, 32, data.regType); // sf
+    setBits(&wrd, 29, 31, data.processOp); // opc
+    setBits(&wrd, 28, 28, data.DPROpType); // M
+    setBits(&wrd, 25 ,28, 0x5);
+    setBits(&wrd, 16, 21, data.src2); // src2 
+    setBits(&wrd, 5, 10, data.src1); // src1
+    setBits(&wrd, 0, 5, data.dest); // src2 
+
+    if (data.DPROpType == a64inst_DPR_MULTIPLY) {
+        setBits(&wrd, 21, 31, 0xD8);
+        setBits(&wrd, 15, 16, data.processOpData.multiplydata.negProd);
+        setBits(&wrd, 10, 15, data.processOpData.multiplydata.summand);
+
+    } else {
+        // Arithmetic Logic Instruction
+        setBits(&wrd, 22, 24, data.processOpData.arithmLogicData.shiftType);
+        setBits(&wrd, 10, 16, data.processOpData.arithmLogicData.shiftAmount);
+
+         if (data.processOpData.arithmLogicData.type == a64inst_DPR_ARITHM) {
+            // Arithmetic
+            setBits(&wrd, 24, 25, 0x1); // bit 24
+         } else {
+            setBits(&wrd, 21, 22, data.processOpData.arithmLogicData.negShiftedSrc2);
+         }
+
     }
-    // arithmetic and logical
-    else {
-        // shift
-        opr += 2 * data.processOpData.arithmLogicData.shiftType;
-        // arithmetic
-        if (data.processOpData.arithmLogicData.type == 1) {
-            opr += 8;
-        }
-        // logical
-        else {
-            if (data.processOpData.arithmLogicData.negShiftedSrc2) {
-                opr += 1;
-            }
-        }
-        operand += data.processOpData.arithmLogicData.shiftAmount;
-    }
-    rm += data.src1;
-    rn += data.src2;
-    rd += data.dest;
-    out += sf * (1 << 31);
-    out += opc * (1 << 29);
-    out += m * (1 << 28);
-    out += opr * (1 << 21);
-    out += rm * (1 << 16);
-    out += operand * 1024;
-    out += rn * 32;
-    out += rd;
-    return out;
+
+    return wrd;
+    
 }
 
 word sts(a64inst_instruction cI) {