add detail to assembly skeleton

This commit is contained in:
EDiasAlberto 2024-06-04 03:07:00 +01:00
parent 422b0f3e62
commit bb3218b535
2 changed files with 32 additions and 3 deletions

View File

@ -22,6 +22,7 @@ void classifyOpcode(char* opcode, a64inst_instruction *instr){
instr->type = a64inst_SINGLETRANSFER; instr->type = a64inst_SINGLETRANSFER;
} else { } else {
//data processing //data processing
} }
} }
@ -52,12 +53,12 @@ a64inst_instruction *parser(char asmLine[]){
char *opcode = strtok(stringptr, " "); char *opcode = strtok(stringptr, " ");
char *operands = strtok(NULL, ""); char *operands = strtok(NULL, "");
if(opcode[0]=="."){ if(strcmp(opcode, ".int") == 0){
//type is directive //type is directive
//define new type in a64instr struct //define new type in a64instr struct
} else if(opcode[strlen(opcode)-1]==":") { } else if(strcmp(opcode[strlen(opcode)-1], ":") == 0) {
//type is label //type is label
//use symbol table to assemble //add to symbol table
} else { } else {
//type is instruction //type is instruction
int operandCount = 0; int operandCount = 0;

View File

@ -10,3 +10,31 @@ void generateSymbolTable(a64inst_instruction instrs[], int numInstrs){
} }
} }
} }
word assembleBranch(a64inst_instruction *instr){
word binInstr = 0;
switch (instr->data.BranchData.BranchType)
{
case a64inst_UNCONDITIONAL:
//000101
//25-0: sign extended simm26
break;
case a64inst_REGISTER:
//1101011
//0000
//11111
//000000
//9-5: address from register
//0000
break;
case a64inst_CONDITIONAL:
// 01010100
// 25-5: sign extended offset
// 4-0: 0{condition}
break;
default:
break;
}
}