From bb3218b53588b11aedf6b978ff9679632b7f4389 Mon Sep 17 00:00:00 2001 From: EDiasAlberto Date: Tue, 4 Jun 2024 03:07:00 +0100 Subject: [PATCH] add detail to assembly skeleton --- src/parser.c | 7 ++++--- src/twopassassembly.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/parser.c b/src/parser.c index 4961480..e944ebc 100644 --- a/src/parser.c +++ b/src/parser.c @@ -22,6 +22,7 @@ void classifyOpcode(char* opcode, a64inst_instruction *instr){ instr->type = a64inst_SINGLETRANSFER; } else { //data processing + } } @@ -52,12 +53,12 @@ a64inst_instruction *parser(char asmLine[]){ char *opcode = strtok(stringptr, " "); char *operands = strtok(NULL, ""); - if(opcode[0]=="."){ + if(strcmp(opcode, ".int") == 0){ //type is directive //define new type in a64instr struct - } else if(opcode[strlen(opcode)-1]==":") { + } else if(strcmp(opcode[strlen(opcode)-1], ":") == 0) { //type is label - //use symbol table to assemble + //add to symbol table } else { //type is instruction int operandCount = 0; diff --git a/src/twopassassembly.c b/src/twopassassembly.c index 24080f3..d2536dd 100644 --- a/src/twopassassembly.c +++ b/src/twopassassembly.c @@ -10,3 +10,31 @@ void generateSymbolTable(a64inst_instruction instrs[], int numInstrs){ } } } + +word assembleBranch(a64inst_instruction *instr){ + word binInstr = 0; + switch (instr->data.BranchData.BranchType) + { + case a64inst_UNCONDITIONAL: + //000101 + //25-0: sign extended simm26 + + break; + case a64inst_REGISTER: + //1101011 + //0000 + //11111 + //000000 + //9-5: address from register + //0000 + + break; + case a64inst_CONDITIONAL: + // 01010100 + // 25-5: sign extended offset + // 4-0: 0{condition} + break; + default: + break; + } +}