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Fix bugs to make code compile. Code now compiles

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This commit is contained in:
sBubshait 2024-06-11 23:19:04 +01:00
parent 31c1ae90f7
commit 999f36facd
2 changed files with 60 additions and 110 deletions
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49
src/symboltable.h
View File

@ -1,49 +0,0 @@
#include <stdio.h>
typedef struct st st;
typedef struct {
const void* key;
void* value;
node* prev;
node* next;
} node;
struct st {
node* head;
node* tail;
};
// add new node to the end
void st_add(st table, void* key, void* value) {
node n = {key, value, table.tail};
if (table.head == NULL) {
table.head = &n;
table.tail = &n;
}
else {
(*(table.tail)).next = &n;
table.tail = &n;
}
}
// returns the pointer to key of the specified node, or null, if it does not exist
void* st_search(st table, void* key) {
return nodeSearch(table.head, key);
}
void* nodeSearch(node* n, void* key) {
if (n != NULL) {
if ((*n).key == key) {
return (*n).value;
}
else {
return nodeSearch((*n).next, key);
}
}
else {
return NULL;
}
}

117
src/twopassassembly.c
View File

@ -1,32 +1,33 @@
#include "global.h" #include "global.h"
#include "a64instruction/a64instruction.h" #include "a64instruction/a64instruction.h"
#include "symboltable.c" #include "symboltable.c"
//generates assembled code based on two pass assembly method #include <stdlib.h>
#include <limits.h>
// Generates assembled code based on the two-pass assembly method
word assembleBranch(a64inst_instruction *instr){ word assembleBranch(a64inst_instruction *instr) {
word binInstr = 0; word binInstr = 0;
binInstr += (5^28); //101 start of branch instr binInstr += (5 << 28); // 101 start of branch instr
switch (instr->data.BranchData.BranchType) switch (instr->data.BranchData.BranchType) {
{
case a64inst_UNCONDITIONAL: case a64inst_UNCONDITIONAL:
//000101 // 000101
//25-0: sign extended simm26 // 25-0: sign extended simm26
binInstr += instr->data.BranchData.processOpData.unconditionalData.unconditionalOffset; binInstr += instr->data.BranchData.processOpData.unconditionalData.unconditionalOffset;
break; break;
case a64inst_REGISTER: case a64inst_REGISTER:
//10000 // 10000
//11111 // 11111
//000000 // 000000
//9-5: address from register // 9-5: address from register
//0000 // 0000
binInstr += ((instr->data.BranchData.processOpData.registerData.src)^5); binInstr += ((instr->data.BranchData.processOpData.registerData.src) << 5);
break; break;
case a64inst_CONDITIONAL: case a64inst_CONDITIONAL:
// 01010100 // 01010100
// 25-5: sign extended offset // 25-5: sign extended offset
// 4-0: 0{condition} // 4-0: 0{condition}
binInstr += ((instr->data.BranchData.processOpData.conditionalData.offset)^5); binInstr += ((instr->data.BranchData.processOpData.conditionalData.offset) << 5);
binInstr += instr->data.BranchData.processOpData.conditionalData.cond; binInstr += instr->data.BranchData.processOpData.conditionalData.cond;
break; break;
default: default:
@ -35,43 +36,43 @@ word assembleBranch(a64inst_instruction *instr){
return binInstr; return binInstr;
} }
st* firstPass(a64inst_instruction instrs[], int numInstrs){ st* firstPass(a64inst_instruction instrs[], int numInstrs) {
//TODO: // TODO:
// -iterate over instructions, adding to symbol table // -iterate over instructions, adding to symbol table
// create symbol table and map labels to addresses/lines // create symbol table and map labels to addresses/lines
struct st table; st *table = (st*)malloc(sizeof(st));
for(int i=0; i<numInstrs; i++){ for (int i = 0; i < numInstrs; i++) {
// discuss defining a LABEL type // discuss defining a LABEL type
if(instrs[i].type==a64inst_LABEL){ if (instrs[i].type == a64inst_LABEL) {
st_add(table, &(instrs[i].data.LabelData.label), &i); st_add(*table, &(instrs[i].data.LabelData.label), &i);
} }
} }
return &table; return table;
} }
word dpi(a64inst_instruction cI) { word dpi(a64inst_instruction cI) {
word out = 0; word out = 0;
a64inst_DPImmediateData data = cI.data.DPImmediateData; a64inst_DPImmediateData data = cI.data.DPImmediateData;
//sf // sf
out += data.regType*(2^31); out += data.regType * (1 << 31);
out += data.processOp*(2^29); out += data.processOp * (1 << 29);
out += 2^28; out += 1 << 28;
// if arithmetic // if arithmetic
if (data.DPIOpType == a64inst_DPI_ARITHM) { if (data.DPIOpType == a64inst_DPI_ARITHM) {
out += 2^24; out += 1 << 24;
// shift // shift
if (data.processOpData.arithmData.shiftImmediate){ if (data.processOpData.arithmData.shiftImmediate) {
out += 2^22; out += 1 << 22;
} }
out += data.processOpData.arithmData.immediate*(2^10); out += data.processOpData.arithmData.immediate * (1 << 10);
out += data.processOpData.arithmData.src*(2^5); out += data.processOpData.arithmData.src * (1 << 5);
} }
// if wide move // if wide move
else { else {
out += 5*(2^23); out += 5 * (1 << 23);
// hw // hw
out += data.processOpData.wideMovData.shiftScalar*(2^21); out += data.processOpData.wideMovData.shiftScalar * (1 << 21);
out += data.processOpData.wideMovData.immediate*(2^5); out += data.processOpData.wideMovData.immediate * (1 << 5);
} }
// destination register // destination register
out += data.dest; out += data.dest;
@ -84,7 +85,7 @@ word dpr(a64inst_instruction cI) {
// sf // sf
int sf = data.regType; int sf = data.regType;
// bits 27-25 // bits 27-25
out += 5*(2^25); out += 5 * (1 << 25);
int m = data.DPROpType; int m = data.DPROpType;
int opc = 0; int opc = 0;
int opr = 0; int opr = 0;
@ -94,7 +95,7 @@ word dpr(a64inst_instruction cI) {
int rd = 0; int rd = 0;
// multiply // multiply
if (m == 1) { if (m == 1) {
//opc = 0; // opc = 0;
opr = 8; opr = 8;
if (data.processOpData.multiplydata.negProd) { if (data.processOpData.multiplydata.negProd) {
operand += 32; operand += 32;
@ -104,9 +105,9 @@ word dpr(a64inst_instruction cI) {
// arithmetic and logical // arithmetic and logical
else { else {
// shift // shift
opr += 2*data.processOpData.arithmLogicData.shiftType; opr += 2 * data.processOpData.arithmLogicData.shiftType;
// arithmetic // arithmetic
if (data.processOpData.arithmLogicData.type == 1){ if (data.processOpData.arithmLogicData.type == 1) {
opr += 8; opr += 8;
} }
// logical // logical
@ -120,11 +121,11 @@ word dpr(a64inst_instruction cI) {
rm += data.src1; rm += data.src1;
rn += data.src2; rn += data.src2;
rd += data.dest; rd += data.dest;
out += sf*(2^31); out += sf * (1 << 31);
out += opc * (2^29); out += opc * (1 << 29);
out += m* (2^28); out += m * (1 << 28);
out += opr * (2^21); out += opr * (1 << 21);
out += rm * (2^16); out += rm * (1 << 16);
out += operand * 1024; out += operand * 1024;
out += rn * 32; out += rn * 32;
out += rd; out += rd;
@ -136,17 +137,16 @@ word sts(a64inst_instruction cI) {
word out = 0; word out = 0;
a64inst_SingleDataTransferData data2 = data.processOpData.singleDataTransferData; a64inst_SingleDataTransferData data2 = data.processOpData.singleDataTransferData;
// this deals with every bit in the 31-23 range apart from sf and U // this deals with every bit in the 31-23 range apart from sf and U
out += (512+128+64+32)*(2^23); out += (512 + 128 + 64 + 32U) * (1 << 23);
int sf = data.regType; int sf = data.regType;
int u = 0; int u = 0;
int l = data2.transferType;
int offset = 0; int offset = 0;
int xn = data2.base; int xn = data2.base;
int rt = data.target; int rt = data.target;
switch (data2.addressingMode) { switch (data2.addressingMode) {
// register offset // register offset
case 2: case 2:
offset += 2074 + 64*data2.a64inst_addressingModeData.offsetReg; offset += 2074 + 64 * data2.a64inst_addressingModeData.offsetReg;
break; break;
// unsigned offset // unsigned offset
case 3: case 3:
@ -155,37 +155,36 @@ word sts(a64inst_instruction cI) {
break; break;
// pre/post indexed // pre/post indexed
default: default:
offset = 1 + data2.addressingMode*2 + data2.a64inst_addressingModeData.indexedOffset*4; offset = 1 + data2.addressingMode * 2 + data2.a64inst_addressingModeData.indexedOffset * 4;
break; break;
} }
out += sf*(2^30); out += sf * (1 << 30);
out += u*(2^22); out += u * (1 << 22);
out += offset*1024; out += offset * 1024;
out += xn * 32; out += xn * 32;
out += rt; out += rt;
return out; return out;
} }
word ldl(a64inst_instruction cI) { word ldl(a64inst_instruction cI) {
word out = 3*(2^27); word out = 3 * (1 << 27);
a64inst_SingleTransferData data = cI.data.SingleTransferData; a64inst_SingleTransferData data = cI.data.SingleTransferData;
int sf = data.regType; int sf = data.regType;
int simm19 = data.processOpData.loadLiteralData.offset; int simm19 = data.processOpData.loadLiteralData.offset;
int rt = data.target; int rt = data.target;
out += sf * (2^30); out += sf * (1 << 30);
out += simm19*32; out += simm19 * 32;
out += rt; out += rt;
return out; return out;
} }
void secondPass(a64inst_instruction instrs[], int numInstrs, st* table, word arr[]){ void secondPass(a64inst_instruction instrs[], int numInstrs, st* table, word arr[]) {
//TODO: // TODO:
// iterate over instructions again, this time replacing labels // iterate over instructions again, this time replacing labels
// with values from symbol table // with values from symbol table
// after a line has had all the values replaced, assemble it and append // after a line has had all the values replaced, assemble it and append
int index = 0; int index = 0;
int lbl = 0; for (int i = 0; i < numInstrs; i++) {
for (int i=0; i<numInstrs; i++) {
a64inst_instruction cI = instrs[i]; a64inst_instruction cI = instrs[i];
switch (cI.type) { switch (cI.type) {
case a64inst_DPIMMEDIATE: case a64inst_DPIMMEDIATE:
@ -209,11 +208,11 @@ void secondPass(a64inst_instruction instrs[], int numInstrs, st* table, word arr
index++; index++;
break; break;
case a64inst_HALT: case a64inst_HALT:
arr[index] = 69*(2^25); arr[index] = 69U * (1 << 25);
index++; index++;
break; break;
case a64inst_LABEL: case a64inst_LABEL:
lbl++; // Labels are handled in the first pass and used for addressing.
break; break;
case a64inst_BRANCH: case a64inst_BRANCH:
arr[index] = assembleBranch(&cI); arr[index] = assembleBranch(&cI);