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Merge branch 'assembler-e' into 'assembler'

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rewrite logic for DP classification and struct access

See merge request lab2324_summer/armv8_43!6
This commit is contained in:
Dias Alberto, Ethan 2024-06-06 16:55:21 +00:00
commit 34dd5706a5
2 changed files with 38 additions and 26 deletions
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56
src/parser.c
View File

@ -1,5 +1,6 @@
#include <stdio.h> #include <stdio.h>
#include <string.h> #include <string.h>
#include <stdbool.h>
#include "parser.h" #include "parser.h"
#include "a64instruction.h" #include "a64instruction.h"
@ -13,35 +14,36 @@
// - match opcode to a64 struct types (DONE) // - match opcode to a64 struct types (DONE)
// - count operands and match type/values // - count operands and match type/values
// - generate final a64inst and return // - generate final a64inst and return
// - CREATE FUNC TO TIDY UP OPERANDS IN DP
//calculate offsets from string //calculate offsets from string
void calcluateAddressFormat(a64inst_instruction *instr, char *operandList[]){ void calcluateAddressFormat(a64inst_instruction *instr, char *operandList[]){
if(strcmp(operandList[2][strlen(operandList[1])-1], "!")==0){ if(strcmp(operandList[2][strlen(operandList[1])-1], "!")==0){
instr->data.processOpData.addressingMode = a64inst_PRE_INDEXED; instr->data.SingleTransferData.processOpData.singleDataTransferData.addressingMode = a64inst_PRE_INDEXED;
} else if(strcmp(operandList[1][strlen(operandList[0])-1], "]") == 0) { } else if(strcmp(operandList[1][strlen(operandList[0])-1], "]") == 0) {
//post-indexed //post-indexed
instr->data.processOpData.addressingMode = a64inst_POST_INDEXED; instr->data.SingleTransferData.processOpData.singleDataTransferData.addressingMode = a64inst_POST_INDEXED;
} else if( (strcmp(operandList[2][strlen(operandList[1])-1], "x") == 0) } else if( (strcmp(operandList[2][strlen(operandList[1])-1], "x") == 0)
|| (strcmp(operandList[2][strlen(operandList[1])-1], "w") == 0)){ || (strcmp(operandList[2][strlen(operandList[1])-1], "w") == 0)){
//register //register
instr->data.processOpData.addressingMode = a64inst_REGISTER_OFFSET; instr->data.SingleTransferData.processOpData.singleDataTransferData.processOpData.addressingMode = a64inst_REGISTER_OFFSET;
} else { } else {
instr->data.processOpData.addressingMode = a64inst_UNSIGNED_OFFSET; instr->data.SingleTransferData.processOpData.singleDataTransferData.addressingMode = a64inst_UNSIGNED_OFFSET;
} }
} }
void generateLoadStoreOperands(a64inst_instruction *instr, char *opcode, char *operandList[]){ void generateLoadStoreOperands(a64inst_instruction *instr, char *opcode, char *operandList[]){
switch(instr->data.type){ switch(instr->type){
case a64inst_SINGLETRANSFER: case a64inst_SINGLETRANSFER:
if(strcmp(operandList[0][0], "x")==0){ if(strcmp(operandList[0][0], "x")==0){
//x-register //x-register
instr->data.regType = 1; instr->data.SingleTransferData.regType = 1;
} else { } else {
instr->data.regType = 0; instr->data.SingleTransferData.regType = 0;
} }
char *endptr; char *endptr;
instr->data.target = strtol(operandList[0][0]+1, endptr, 2); instr->data.SingleTransferData.target = strtol(operandList[0][0]+1, endptr, 2);
calcluateAddressFormat(instr, operandList); calcluateAddressFormat(instr, operandList);
break; break;
case a64inst_LOADLITERAL: case a64inst_LOADLITERAL:
@ -51,38 +53,48 @@ void generateLoadStoreOperands(a64inst_instruction *instr, char *opcode, char *o
} }
void generateBranchOperands(a64inst_instruction *instr, char* opcode, char *operandList[]){ void generateBranchOperands(a64inst_instruction *instr, char* opcode, char *operandList[]){
switch(instr->data.BranchType){ switch(instr->data.BranchData.BranchType){
case a64inst_UNCONDITIONAL: case a64inst_UNCONDITIONAL:
//define and sign extend immediate offset //define and sign extend immediate offset
//use symbol table //use symbol table
break; break;
case a64inst_REGISTER: case a64inst_REGISTER:
char *endptr; char *endptr;
instr->data.processOpData.src = strtol(operandList[0] + 1, endptr, 2) instr->data.BranchData.processOpData.registerData.src = strtol(operandList[0] + 1, endptr, 2)
break; break;
case a64inst_CONDITIONAL: case a64inst_CONDITIONAL:
char* condition = strtok(strdup(opcode), "b."); char* condition = strtok(strdup(opcode), "b.");
condition = strtok(NULL, ""); condition = strtok(NULL, "");
if(strcmp(condition, "eq")==0){ if(strcmp(condition, "eq")==0){
instr->data.processOpData.cond = EQ; instr->data.branchData.processOpData.conditionalData.cond = EQ;
} else if (strcmp(condition, "ne")==0){ } else if (strcmp(condition, "ne")==0){
instr->data.processOpData.cond = NE; instr->data.branchData.processOpData.conditionalData.cond = NE;
} else if (strcmp(condition, "ge")==0){ } else if (strcmp(condition, "ge")==0){
instr->data.processOpData.cond = GE; instr->data.branchData.processOpData.conditionalData.cond = GE;
} else if (strcmp(condition, "lt")==0){ } else if (strcmp(condition, "lt")==0){
instr->data.processOpData.cond = LT; instr->data.branchData.processOpData.conditionalData.cond = LT;
} else if (strcmp(condition, "gt")==0){ } else if (strcmp(condition, "gt")==0){
instr->data.processOpData.cond = GT; instr->data.branchData.processOpData.conditionalData.cond = GT;
} else if (strcmp(condition, "le")==0){ } else if (strcmp(condition, "le")==0){
instr->data.processOpData.cond = LE; instr->data.branchData.processOpData.conditionalData.cond = LE;
} else if (srtcmp(condition, "al")==0){ } else if (srtcmp(condition, "al")==0){
instr->data.processOpData.cond = AL; instr->data.branchData.processOpData.conditionalData.cond = AL;
} }
break; break;
//calculate offset from symbol table. //calculate offset from symbol table.
} }
} }
int isOperandRegister(char *operand){
return((strcmp(operand[0], "x")==0) || (strcmp(operand[0], "w")==0));
}
int classifyDPInst(char *operandList[]){
return(isOperandRegister(operandList[0]) &&
isOperandRegister(operandList[1]) &&
isOperandRegister(operandList[2]));
}
void classifyOpcode(char* opcode, a64inst_instruction *instr, char *operandList[]){ void classifyOpcode(char* opcode, a64inst_instruction *instr, char *operandList[]){
int isUnconditional = strcmp(opcode, "b"); int isUnconditional = strcmp(opcode, "b");
int isRegister = strcmp(opcode, "br"); int isRegister = strcmp(opcode, "br");
@ -108,11 +120,11 @@ void classifyOpcode(char* opcode, a64inst_instruction *instr, char *operandList[
if( *address == '['){ if( *address == '['){
//type is register //type is register
instr->type = a64inst_SINGLETRANSFER; instr->type = a64inst_SINGLETRANSFER;
instr->data.SingleTransferOpType = a64inst_SINGLE_TRANSFER_SINGLE_DATA_TRANSFER; instr->data.singleTransferData.SingleTransferOpType = a64inst_SINGLE_TRANSFER_SINGLE_DATA_TRANSFER;
if(isLoad == 0){ if(isLoad == 0){
instr->data.processOpData.transferType = a64inst_LOAD; instr->data.SingleTransferData.transferType = a64inst_LOAD;
} else { } else {
instr->data.processOpData.transferType = a64inst_STORE; instr->data.SingleTransferData.processOpData.transferType = a64inst_STORE;
} }
} else { } else {
instr->type = a64inst_LOADLITERAL; instr->type = a64inst_LOADLITERAL;
@ -121,7 +133,7 @@ void classifyOpcode(char* opcode, a64inst_instruction *instr, char *operandList[
} else { } else {
int numOperands = sizeof(operandList) / sizeof(operandList[0]) int numOperands = sizeof(operandList) / sizeof(operandList[0])
if(numOperands==3){ if(classifyDPInst(operandList)){
instr->type = a64inst_DPREGISTER; instr->type = a64inst_DPREGISTER;
} else { } else {
instr->type = a64inst_DPIMMEDIATE; instr->type = a64inst_DPIMMEDIATE;
@ -172,7 +184,7 @@ a64inst_instruction *parser(char asmLine[]){
instr->type = a64inst_LABEL; instr->type = a64inst_LABEL;
char *opcodeCpy = strdup(opcode); char *opcodeCpy = strdup(opcode);
char *labelData = strtok(opcodeCpy, ":"); char *labelData = strtok(opcodeCpy, ":");
instr->data.label = labelData; instr->data.labelData.label = labelData;
} else { } else {
//type is instruction //type is instruction
int operandCount = 0; int operandCount = 0;

8
src/twopassassembly.c
View File

@ -49,7 +49,7 @@ st* firstPass(a64inst_instruction instrs[], int numInstrs){
} }
return &table; return &table;
} }
word dpi(a64inst_instruction cI) { word assembleDPI(a64inst_instruction cI) {
word out = 0; word out = 0;
a64inst_DPImmediateData data = cI.data.DPImmediateData; a64inst_DPImmediateData data = cI.data.DPImmediateData;
//sf //sf
@ -78,7 +78,7 @@ word dpi(a64inst_instruction cI) {
return out; return out;
} }
word dpr(a64inst_instruction cI) { word assembleDPR(a64inst_instruction cI) {
word out = 0; word out = 0;
a64inst_DPRegisterData data = cI.data.DPRegisterData; a64inst_DPRegisterData data = cI.data.DPRegisterData;
// sf // sf
@ -131,7 +131,7 @@ word dpr(a64inst_instruction cI) {
return out; return out;
} }
word sts(a64inst_instruction cI) { word assembleSTS(a64inst_instruction cI) {
a64inst_SingleTransferData data = cI.data.SingleTransferData; a64inst_SingleTransferData data = cI.data.SingleTransferData;
word out = 0; word out = 0;
a64inst_SingleDataTransferData data2 = data.processOpData.singleDataTransferData; a64inst_SingleDataTransferData data2 = data.processOpData.singleDataTransferData;
@ -166,7 +166,7 @@ word sts(a64inst_instruction cI) {
return out; return out;
} }
word ldl(a64inst_instruction cI) { word assembleLDL(a64inst_instruction cI) {
word out = 3*(2^27); word out = 3*(2^27);
a64inst_SingleTransferData data = cI.data.SingleTransferData; a64inst_SingleTransferData data = cI.data.SingleTransferData;
int sf = data.regType; int sf = data.regType;