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single data transfer & load literal

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GDBWNV 2024-06-06 13:34:14 +01:00
parent 09956c7b2e
commit 1440ebd702
1 changed files with 53 additions and 0 deletions
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53
src/twopassassembly.c
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@ -128,6 +128,53 @@ word dpr(a64inst_instruction cI) {
return out;
}
word sts(a64inst_instruction cI) {
a64inst_SingleTransferData data = cI.data.SingleTransferData;
word out = 0;
a64inst_SingleDataTransferData data2 = data.processOpData.singleDataTransferData;
// this deals with every bit in the 31-23 range apart from sf and U
out += (512+128+64+32)*(2^23);
int sf = data.regType;
int u = 0;
int l = data2.transferType;
int offset = 0;
int xn = data2.base;
int rt = data.target;
switch (data2.addressingMode) {
// register offset
case 2:
offset += 2074 + 64*data2.a64inst_addressingModeData.offsetReg;
break;
// unsigned offset
case 3:
offset += data2.a64inst_addressingModeData.unsignedOffset;
u = 1;
break;
// pre/post indexed
default:
offset = 1 + data2.addressingMode*2 + data2.a64inst_addressingModeData.indexedOffset*4;
break;
}
out += sf*(2^30);
out += u*(2^22);
out += offset*1024;
out += xn * 32;
out += rt;
return out;
}
word ldl(a64inst_instruction cI) {
word out = 3*(2^27);
a64inst_SingleTransferData data = cI.data.SingleTransferData;
int sf = data.regType;
int simm19 = data.processOpData.loadLiteralData.offset;
int rt = data.target;
out += sf * (2^30);
out += simm19*32;
out += rt;
return out;
}
void secondPass(a64inst_instruction instrs[], int numInstrs, st* table){
//TODO:
// iterate over instructions again, this time replacing labels
@ -142,6 +189,12 @@ void secondPass(a64inst_instruction instrs[], int numInstrs, st* table){
case a64inst_DPREGISTER:
dpr(cI);
break;
case a64inst_SINGLETRANSFER:
sts(cI);
break;
case a64inst_LOADLITERAL:
ldl(cI);
break;
default:
break;
}