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data processing register

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GDBWNV 2024-06-06 13:00:27 +01:00
parent ce34f27fbd
commit 09956c7b2e
1 changed files with 56 additions and 0 deletions
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56
src/twopassassembly.c
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@ -75,6 +75,59 @@ word dpi(a64inst_instruction cI) {
return out;
}
word dpr(a64inst_instruction cI) {
word out = 0;
a64inst_DPRegisterData data = cI.data.DPRegisterData;
// sf
int sf = data.regType;
// bits 27-25
out += 5*(2^25);
int m = data.DPROpType;
int opc = 0;
int opr = 0;
int rm = 0;
int operand = 0;
int rn = 0;
int rd = 0;
// multiply
if (m == 1) {
//opc = 0;
opr = 8;
if (data.processOpData.multiplydata.negProd) {
operand += 32;
}
operand += data.processOpData.multiplydata.summand;
}
// arithmetic and logical
else {
// shift
opr += 2*data.processOpData.arithmLogicData.shiftType;
// arithmetic
if (data.processOpData.arithmLogicData.type == 1){
opr += 8;
}
// logical
else {
if (data.processOpData.arithmLogicData.negShiftedSrc2) {
opr += 1;
}
}
operand += data.processOpData.arithmLogicData.shiftAmount;
}
rm += data.src1;
rn += data.src2;
rd += data.dest;
out += sf*(2^31);
out += opc * (2^29);
out += m* (2^28);
out += opr * (2^21);
out += rm * (2^16);
out += operand * 1024;
out += rn * 32;
out += rd;
return out;
}
void secondPass(a64inst_instruction instrs[], int numInstrs, st* table){
//TODO:
// iterate over instructions again, this time replacing labels
@ -86,6 +139,9 @@ void secondPass(a64inst_instruction instrs[], int numInstrs, st* table){
case a64inst_DPIMMEDIATE:
dpi(cI);
break;
case a64inst_DPREGISTER:
dpr(cI);
break;
default:
break;
}