diff --git a/src/execute.c b/src/execute.c index 4ef7512..2d60bef 100644 --- a/src/execute.c +++ b/src/execute.c @@ -362,7 +362,7 @@ void execute_SDT(Machine *state, a64inst_instruction *inst) { if (inst->data.SingleTransferData.SingleTransferOpType == a64inst_SINGLE_TRANSFER_LOAD_LITERAL) { // Load Literal isLoad = true; - address = state->pc + inst->data.SingleTransferData.processOpData.loadLiteralData.offset * 4; + address = state->pc + signExtend(inst->data.SingleTransferData.processOpData.loadLiteralData.offset, 19) * 4; } else { address = state->registers[inst->data.SingleTransferData.processOpData.singleDataTransferData.base]; isLoad = inst->data.SingleTransferData.processOpData.singleDataTransferData.transferType == a64inst_LOAD; @@ -374,7 +374,7 @@ void execute_SDT(Machine *state, a64inst_instruction *inst) { address += state->registers[inst->data.SingleTransferData.processOpData.singleDataTransferData.a64inst_addressingModeData.offsetReg]; break; case a64inst_PRE_INDEXED: - address += inst->data.SingleTransferData.processOpData.singleDataTransferData.a64inst_addressingModeData.indexedOffset; + address += signExtend(inst->data.SingleTransferData.processOpData.singleDataTransferData.a64inst_addressingModeData.indexedOffset, 9); state->registers[inst->data.SingleTransferData.processOpData.singleDataTransferData.base] = address; break; case a64inst_POST_INDEXED: @@ -395,7 +395,8 @@ void execute_SDT(Machine *state, a64inst_instruction *inst) { // Update base register if post indexed if (inst->data.SingleTransferData.processOpData.singleDataTransferData.addressingMode == a64inst_POST_INDEXED) { - writeRegister(state, inst->data.SingleTransferData.processOpData.singleDataTransferData.base, inst->data.SingleTransferData.regType == a64inst_W, address + inst->data.SingleTransferData.processOpData.singleDataTransferData.a64inst_addressingModeData.indexedOffset); + dword result = address + signExtend(inst->data.SingleTransferData.processOpData.singleDataTransferData.a64inst_addressingModeData.indexedOffset, 9); + writeRegister(state, inst->data.SingleTransferData.processOpData.singleDataTransferData.base, inst->data.SingleTransferData.regType == a64inst_W, result); } }