Add decode for Branch Instructions, w/ T
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36
src/decode.c
36
src/decode.c
@ -22,7 +22,7 @@ a64inst_instruction *decode(word wrd) {
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exit(1);
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exit(1);
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}
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}
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word DPImmFlag = getBits(wrd, DATA_PROCESSING_DPIMM_LSB, DATA_PROCESSING_DPIMM_MSB);
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word DPImmFlag = getBits(wrd, BRANCH_CONDITIONAL_COND_LSB, BRANCH_CONDITIONAL_COND_MSB);
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if (wrd == HALT_WORD) {
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if (wrd == HALT_WORD) {
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inst->type = a64inst_HALT;
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inst->type = a64inst_HALT;
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@ -31,8 +31,40 @@ a64inst_instruction *decode(word wrd) {
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}else if (DPImmFlag == 1) {
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}else if (DPImmFlag == 1) {
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inst->type = a64inst_BRANCH;
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inst->type = a64inst_BRANCH;
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word branchTypeFlag = getBits(wrd, BRANCH_TYPE_LSB, BRANCH_TYPE_MSB);
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inst->data.BranchData.BranchType = branchTypeFlag;
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} else if (getBits(wrd, DATA_PROCESSING_DPREG_LSB, DATA_PROCESSING_DPREG_MSB) == 1) {
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switch (branchTypeFlag) {
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case a64inst_UNCONDITIONAL:
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inst->data.BranchData.processOpData.unconditionalData.unconditionalOffset = getBits(wrd, BRANCH_UNCONDITIONAL_OFFSET_LSB, BRANCH_UNCONDITIONAL_OFFSET_MSB);
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break;
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case a64inst_CONDITIONAL:
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inst->data.BranchData.processOpData.conditionalData.offset = getBits(wrd, BRANCH_CONDITIONAL_OFFSET_LSB, BRANCH_CONDITIONAL_OFFSET_MSB);
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word conditionFlag = getBits(wrd, BRANCH_CONDITIONAL_COND_LSB, BRANCH_CONDITIONAL_COND_MSB);
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if(conditionFlag <= 1 || (conditionFlag >= 10 && conditionFlag <= 14)) {
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inst->data.BranchData.processOpData.conditionalData.cond = conditionFlag;
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} else {
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fprintf(stderr, "Error: Unknown condition detected.\n");
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exit(1);
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}
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break;
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case a64inst_REGISTER:
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inst->data.BranchData.processOpData.registerData.src = getBits(wrd, BRANCH_REGISTER_SRC_LSB, BRANCH_REGISTER_SRC_MSB);
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break;
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default:
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fprintf(stderr, "Undefined branch type detected!\n");
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exit(1);
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break;
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}
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} else if (getBits(wrd, DATA_PROCESSING_REG_LSB, DATA_PROCESSING_REG_MSB) == 1) {
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inst->type = a64inst_DPREGISTER;
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inst->type = a64inst_DPREGISTER;
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} else {
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} else {
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19
src/decode.h
19
src/decode.h
@ -4,10 +4,21 @@
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#define BYTE_BITS 8
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#define BYTE_BITS 8
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#define HALT_WORD 0x8a000000
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#define HALT_WORD 0x8a000000
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#define DATA_PROCESSING_DPIMM_LSB 26
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#define DATA_PROCESSING_IMM_LSB 26
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#define DATA_PROCESSING_DPIMM_MSB 29
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#define DATA_PROCESSING_IMM_MSB 29
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#define DATA_PROCESSING_DPREG_LSB 25
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#define DATA_PROCESSING_REG_LSB 25
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#define DATA_PROCESSING_DPREG_MSB 26
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#define DATA_PROCESSING_REG_MSB 26
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#define BRANCH_TYPE_LSB 30
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#define BRANCH_TYPE_MSB 32
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#define BRANCH_UNCONDITIONAL_OFFSET_LSB 0
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#define BRANCH_UNCONDITIONAL_OFFSET_MSB 26
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#define BRANCH_REGISTER_SRC_LSB 5
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#define BRANCH_REGISTER_SRC_MSB 10
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#define BRANCH_CONDITIONAL_COND_LSB 0
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#define BRANCH_CONDITIONAL_COND_MSB 4
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#define BRANCH_CONDITIONAL_OFFSET_LSB 5
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#define BRANCH_CONDITIONAL_OFFSET_MSB 24
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a64inst_instruction *decode(word w);
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a64inst_instruction *decode(word w);
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