Fix bugs to make code compile. Code now compiles
This commit is contained in:
sBubshait
parent
31c1ae90f7
commit
999f36facd
@ -1,49 +0,0 @@
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#include <stdio.h>
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typedef struct st st;
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typedef struct {
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const void* key;
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void* value;
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node* prev;
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node* next;
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} node;
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struct st {
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node* head;
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node* tail;
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};
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// add new node to the end
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void st_add(st table, void* key, void* value) {
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node n = {key, value, table.tail};
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if (table.head == NULL) {
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table.head = &n;
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table.tail = &n;
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}
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else {
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(*(table.tail)).next = &n;
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table.tail = &n;
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}
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}
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// returns the pointer to key of the specified node, or null, if it does not exist
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void* st_search(st table, void* key) {
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return nodeSearch(table.head, key);
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}
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void* nodeSearch(node* n, void* key) {
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if (n != NULL) {
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if ((*n).key == key) {
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return (*n).value;
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}
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else {
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return nodeSearch((*n).next, key);
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}
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}
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else {
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return NULL;
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}
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}
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@ -1,32 +1,33 @@
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#include "global.h"
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#include "a64instruction/a64instruction.h"
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#include "symboltable.c"
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//generates assembled code based on two pass assembly method
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#include <stdlib.h>
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#include <limits.h>
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// Generates assembled code based on the two-pass assembly method
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word assembleBranch(a64inst_instruction *instr){
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word assembleBranch(a64inst_instruction *instr) {
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word binInstr = 0;
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binInstr += (5^28); //101 start of branch instr
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switch (instr->data.BranchData.BranchType)
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{
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binInstr += (5 << 28); // 101 start of branch instr
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switch (instr->data.BranchData.BranchType) {
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case a64inst_UNCONDITIONAL:
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//000101
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//25-0: sign extended simm26
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// 000101
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// 25-0: sign extended simm26
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binInstr += instr->data.BranchData.processOpData.unconditionalData.unconditionalOffset;
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break;
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case a64inst_REGISTER:
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//10000
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//11111
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//000000
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//9-5: address from register
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//0000
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binInstr += ((instr->data.BranchData.processOpData.registerData.src)^5);
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// 10000
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// 11111
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// 000000
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// 9-5: address from register
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// 0000
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binInstr += ((instr->data.BranchData.processOpData.registerData.src) << 5);
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break;
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case a64inst_CONDITIONAL:
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// 01010100
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// 01010100
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// 25-5: sign extended offset
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// 4-0: 0{condition}
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binInstr += ((instr->data.BranchData.processOpData.conditionalData.offset)^5);
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binInstr += ((instr->data.BranchData.processOpData.conditionalData.offset) << 5);
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binInstr += instr->data.BranchData.processOpData.conditionalData.cond;
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break;
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default:
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@ -35,43 +36,43 @@ word assembleBranch(a64inst_instruction *instr){
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return binInstr;
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}
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st* firstPass(a64inst_instruction instrs[], int numInstrs){
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//TODO:
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st* firstPass(a64inst_instruction instrs[], int numInstrs) {
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// TODO:
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// -iterate over instructions, adding to symbol table
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// create symbol table and map labels to addresses/lines
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struct st table;
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for(int i=0; i<numInstrs; i++){
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st *table = (st*)malloc(sizeof(st));
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for (int i = 0; i < numInstrs; i++) {
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// discuss defining a LABEL type
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if(instrs[i].type==a64inst_LABEL){
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st_add(table, &(instrs[i].data.LabelData.label), &i);
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if (instrs[i].type == a64inst_LABEL) {
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st_add(*table, &(instrs[i].data.LabelData.label), &i);
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}
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}
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return &table;
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return table;
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}
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word dpi(a64inst_instruction cI) {
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word out = 0;
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a64inst_DPImmediateData data = cI.data.DPImmediateData;
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//sf
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out += data.regType*(2^31);
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out += data.processOp*(2^29);
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out += 2^28;
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// sf
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out += data.regType * (1 << 31);
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out += data.processOp * (1 << 29);
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out += 1 << 28;
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// if arithmetic
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if (data.DPIOpType == a64inst_DPI_ARITHM) {
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out += 2^24;
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out += 1 << 24;
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// shift
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if (data.processOpData.arithmData.shiftImmediate){
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out += 2^22;
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if (data.processOpData.arithmData.shiftImmediate) {
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out += 1 << 22;
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}
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out += data.processOpData.arithmData.immediate*(2^10);
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out += data.processOpData.arithmData.src*(2^5);
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out += data.processOpData.arithmData.immediate * (1 << 10);
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out += data.processOpData.arithmData.src * (1 << 5);
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}
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// if wide move
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else {
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out += 5*(2^23);
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out += 5 * (1 << 23);
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// hw
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out += data.processOpData.wideMovData.shiftScalar*(2^21);
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out += data.processOpData.wideMovData.immediate*(2^5);
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out += data.processOpData.wideMovData.shiftScalar * (1 << 21);
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out += data.processOpData.wideMovData.immediate * (1 << 5);
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}
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// destination register
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out += data.dest;
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@ -84,7 +85,7 @@ word dpr(a64inst_instruction cI) {
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// sf
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int sf = data.regType;
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// bits 27-25
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out += 5*(2^25);
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out += 5 * (1 << 25);
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int m = data.DPROpType;
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int opc = 0;
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int opr = 0;
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@ -94,7 +95,7 @@ word dpr(a64inst_instruction cI) {
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int rd = 0;
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// multiply
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if (m == 1) {
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//opc = 0;
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// opc = 0;
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opr = 8;
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if (data.processOpData.multiplydata.negProd) {
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operand += 32;
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@ -104,9 +105,9 @@ word dpr(a64inst_instruction cI) {
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// arithmetic and logical
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else {
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// shift
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opr += 2*data.processOpData.arithmLogicData.shiftType;
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opr += 2 * data.processOpData.arithmLogicData.shiftType;
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// arithmetic
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if (data.processOpData.arithmLogicData.type == 1){
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if (data.processOpData.arithmLogicData.type == 1) {
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opr += 8;
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}
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// logical
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@ -120,11 +121,11 @@ word dpr(a64inst_instruction cI) {
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rm += data.src1;
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rn += data.src2;
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rd += data.dest;
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out += sf*(2^31);
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out += opc * (2^29);
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out += m* (2^28);
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out += opr * (2^21);
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out += rm * (2^16);
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out += sf * (1 << 31);
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out += opc * (1 << 29);
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out += m * (1 << 28);
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out += opr * (1 << 21);
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out += rm * (1 << 16);
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out += operand * 1024;
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out += rn * 32;
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out += rd;
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@ -136,17 +137,16 @@ word sts(a64inst_instruction cI) {
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word out = 0;
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a64inst_SingleDataTransferData data2 = data.processOpData.singleDataTransferData;
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// this deals with every bit in the 31-23 range apart from sf and U
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out += (512+128+64+32)*(2^23);
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out += (512 + 128 + 64 + 32U) * (1 << 23);
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int sf = data.regType;
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int u = 0;
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int l = data2.transferType;
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int offset = 0;
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int xn = data2.base;
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int rt = data.target;
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switch (data2.addressingMode) {
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// register offset
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case 2:
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offset += 2074 + 64*data2.a64inst_addressingModeData.offsetReg;
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offset += 2074 + 64 * data2.a64inst_addressingModeData.offsetReg;
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break;
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// unsigned offset
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case 3:
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@ -155,37 +155,36 @@ word sts(a64inst_instruction cI) {
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break;
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// pre/post indexed
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default:
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offset = 1 + data2.addressingMode*2 + data2.a64inst_addressingModeData.indexedOffset*4;
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offset = 1 + data2.addressingMode * 2 + data2.a64inst_addressingModeData.indexedOffset * 4;
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break;
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}
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out += sf*(2^30);
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out += u*(2^22);
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out += offset*1024;
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out += sf * (1 << 30);
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out += u * (1 << 22);
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out += offset * 1024;
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out += xn * 32;
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out += rt;
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return out;
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}
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word ldl(a64inst_instruction cI) {
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word out = 3*(2^27);
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word out = 3 * (1 << 27);
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a64inst_SingleTransferData data = cI.data.SingleTransferData;
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int sf = data.regType;
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int simm19 = data.processOpData.loadLiteralData.offset;
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int rt = data.target;
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out += sf * (2^30);
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out += simm19*32;
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out += sf * (1 << 30);
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out += simm19 * 32;
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out += rt;
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return out;
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}
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void secondPass(a64inst_instruction instrs[], int numInstrs, st* table, word arr[]){
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//TODO:
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void secondPass(a64inst_instruction instrs[], int numInstrs, st* table, word arr[]) {
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// TODO:
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// iterate over instructions again, this time replacing labels
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// with values from symbol table
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// after a line has had all the values replaced, assemble it and append
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int index = 0;
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int lbl = 0;
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for (int i=0; i<numInstrs; i++) {
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for (int i = 0; i < numInstrs; i++) {
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a64inst_instruction cI = instrs[i];
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switch (cI.type) {
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case a64inst_DPIMMEDIATE:
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@ -209,11 +208,11 @@ void secondPass(a64inst_instruction instrs[], int numInstrs, st* table, word arr
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index++;
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break;
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case a64inst_HALT:
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arr[index] = 69*(2^25);
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arr[index] = 69U * (1 << 25);
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index++;
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break;
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case a64inst_LABEL:
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lbl++;
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// Labels are handled in the first pass and used for addressing.
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break;
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case a64inst_BRANCH:
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arr[index] = assembleBranch(&cI);
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@ -223,4 +222,4 @@ void secondPass(a64inst_instruction instrs[], int numInstrs, st* table, word arr
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}
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}
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return;
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}
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}
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