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fix dpregister to construct IR

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This commit is contained in:
EDiasAlberto 2024-06-13 20:00:55 +01:00
parent 228bfec612
commit 6bd993b29e
1 changed files with 47 additions and 1 deletions
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48
src/parser.c
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@ -23,6 +23,7 @@ static const char *WIDE_MOV_OPCODES[] = {"movn", "movz", "movz", "movk"};
static const char *ARITHMETIC_OPCODES[] = {"add", "adds", "sub", "subs"};
static const char *MULTIPLY_OPCODES[] = {"mul", "madd", "msub", "mneg"};
static const char *SHIFT_TYPE_OPCODES[] = {"lsl", "lsr", "asr", "ror"};
static const char *LOGIC_OPCODES[] = {"and", "ands", "bic", "bics", "eor", "eon", "orr", "orn"};
a64inst_instruction *parse(char **asmLines, int lineCount) {
a64inst_instruction *instructions = malloc(sizeof(a64inst_instruction) * lineCount);
@ -349,7 +350,52 @@ void parseDPRegister(a64inst_instruction *inst, char *tokens[], int tokensCount)
} else {
// Logic
int opcodeCategory = indexStringIn(tokens[0], LOGIC_OPCODES, 8);
switch(opcodeCategory/2){
case 0:
//and
if((tokens[0][strlen(tokens[0])-1]) == 's'){
data->processOp = 3;
} else {
data->processOp = 0;
}
data->processOpData.arithmLogicData.negShiftedSrc2 = 0;
break;
case 1:
//negated AND
if((tokens[0][strlen(tokens[0])-1]) == 's'){
data->processOp = 3;
} else {
data->processOp = 0;
}
data->processOpData.arithmLogicData.negShiftedSrc2 = 1;
break;
case 2:
//XOR
data->processOp = 2;
if(opcodeCategory==4){
data->processOpData.arithmLogicData.negShiftedSrc2 = 0;
} else {
data->processOpData.arithmLogicData.negShiftedSrc2 = 1;
}
break;
case 3:
//OR
data->processOp = 1;
if(opcodeCategory==6){
data->processOpData.arithmLogicData.negShiftedSrc2 = 0;
} else {
data->processOpData.arithmLogicData.negShiftedSrc2 = 1;
}
break;
}
if(tokensCount == 5) {
//has a shift
int numTokens = 0;
char **shiftOperands = tokenise(tokens[4], &numTokens);
data->processOpData.arithmLogicData.shiftType = indexStringIn(shiftOperands[0], SHIFT_TYPE_OPCODES, 4);
data->processOpData.arithmLogicData.shiftAmount = getOperandNumber(shiftOperands[1]);
}
}
}
}