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Change structure of execute module w/ S

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This commit is contained in:
Themis Demetriades 2024-06-12 17:44:12 +01:00
parent 9a6d15ce1c
commit 64a9d72806
1 changed files with 40 additions and 45 deletions
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85
src/emulator/execute.c
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@ -19,7 +19,42 @@
// Prototypes // Prototypes
void execute_SDT(Machine *state, a64inst_instruction *inst); void execute_SDT(Machine *state, a64inst_instruction *inst);
void execute_Branch(Machine *state, a64inst_instruction *inst); void execute_Branch(Machine *state, a64inst_instruction *inst);
void executeMultiply(Machine *state, a64inst_instruction *inst); static void executeDPImmediate(Machine *state, a64inst_instruction *inst);
static void executeDPRegister(Machine *state, a64inst_instruction *inst);
void execute(Machine *state, a64inst_instruction *inst) {
switch (inst->type) {
// Halt the program
case a64inst_HALT:
break;
// Execute a data processing immediate instruction
case a64inst_DPIMMEDIATE:
executeDPImmediate(state, inst);
break;
// Execute a branch instruction
case a64inst_BRANCH:
execute_Branch(state, inst);
break;
// Execute a data processing register instruction
case a64inst_DPREGISTER:
executeDPRegister(state, inst);
break;
case a64inst_SINGLETRANSFER:
execute_SDT(state, inst);
break;
// Unknown instruction
default:
break;
}
}
// Updates N and Z condition codes given the machine and a result value // Updates N and Z condition codes given the machine and a result value
static void updateCondNZ(Machine *state, dword result, a64inst_regType regType) { static void updateCondNZ(Machine *state, dword result, a64inst_regType regType) {
@ -241,7 +276,10 @@ static void executeDPRegister(Machine *state, a64inst_instruction *inst) {
break; break;
// Execute a multiply register data processing instruction // Execute a multiply register data processing instruction
case a64inst_DPR_MULTIPLY: case a64inst_DPR_MULTIPLY:;
dword product = state->registers[inst->data.DPRegisterData.src1] * state->registers[inst->data.DPRegisterData.src2];
dword sum = readRegister(state, inst->data.DPRegisterData.processOpData.multiplydata.summand, inst->data.DPRegisterData.regType) + (inst->data.DPRegisterData.processOpData.multiplydata.negProd ? -product : product);
writeRegister(state, inst->data.DPRegisterData.dest, inst->data.DPRegisterData.regType, sum);
break; break;
// Unknown instruction detected! // Unknown instruction detected!
@ -251,43 +289,6 @@ static void executeDPRegister(Machine *state, a64inst_instruction *inst) {
} }
} }
void execute(Machine *state, a64inst_instruction *inst) {
switch (inst->type) {
// Halt the program
case a64inst_HALT:
break;
// Execute a data processing immediate instruction
case a64inst_DPIMMEDIATE:
executeDPImmediate(state, inst);
break;
// Execute a branch instruction
case a64inst_BRANCH:
execute_Branch(state, inst);
break;
// Execute a data processing register instruction
case a64inst_DPREGISTER:
if (inst->data.DPRegisterData.DPROpType == a64inst_DPR_MULTIPLY)
executeMultiply(state, inst);
else
executeDPRegister(state, inst);
break;
case a64inst_SINGLETRANSFER:
execute_SDT(state, inst);
break;
// Unknown instruction
default:
break;
}
}
void execute_SDT(Machine *state, a64inst_instruction *inst) { void execute_SDT(Machine *state, a64inst_instruction *inst) {
word address; word address;
bool isLoad; bool isLoad;
@ -377,9 +378,3 @@ void execute_Branch(Machine *state, a64inst_instruction *inst) {
break; break;
} }
} }
void executeMultiply(Machine *state, a64inst_instruction *inst) {
dword product = state->registers[inst->data.DPRegisterData.src1] * state->registers[inst->data.DPRegisterData.src2];
dword sum = readRegister(state, inst->data.DPRegisterData.processOpData.multiplydata.summand, inst->data.DPRegisterData.regType) + (inst->data.DPRegisterData.processOpData.multiplydata.negProd ? -product : product);
writeRegister(state, inst->data.DPRegisterData.dest, inst->data.DPRegisterData.regType, sum);
}