Restructure encode into a separate module
This commit is contained in:
sBubshait
parent
664f8e6478
commit
38951db9c8
6
src/assemble.c
Executable file → Normal file
6
src/assemble.c
Executable file → Normal file
@ -23,11 +23,11 @@ int main(int argc, char **argv) {
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// First Pass: Create the symbol table
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st *table = firstPass(instructions, lineCount);
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// Second Pass: Assemble the instructions
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word *binary = secondPass(instructions, lineCount, table); // 1000 is just a temp fix.
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// Second Pass: Encode the instructions into binary
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word *binary = encode(instructions, lineCount, table);
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// Write the binary to the output file
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writeBinaryFile(binary, argv[2], lineCount); // 1000 is just a temp fix.
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writeBinaryFile(binary, argv[2], lineCount);
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/* TODO: FREE MEMORY!! */
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224
src/encode.c
Normal file
224
src/encode.c
Normal file
@ -0,0 +1,224 @@
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#include <assert.h>
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#include "global.h"
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#include "a64instruction/a64instruction.h"
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#include "symboltable.c"
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#include <stdlib.h>
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#include <limits.h>
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#define HALT_BINARY 2315255808
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// write the provided value to the bits in the range [lsb, msb) {inclusive, exclusive} to the word.
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// Does not modify any other bits in the word.
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void setBits(word* wrd, uint8_t lsb, uint8_t msb, word value) {
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// Ensure LSB and MSB are within range of word size, and in the correct order
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assert(lsb < msb && msb <= 32);
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// Create a mask with 1s in the range [lsb, msb) and 0s elsewhere
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word mask = 0;
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for (uint8_t i = lsb; i < msb; i++) {
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mask |= 1 << i;
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}
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// Clear the bits in the range [lsb, msb) in the word
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*wrd &= ~mask;
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// Set the bits in the range [lsb, msb) to the value
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*wrd |= (value << lsb) & mask;
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}
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// Generates assembled code based on the two-pass assembly method
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word encodeBranch(a64inst_instruction *instr) {
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word wrd = 0;
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switch (instr->data.BranchData.BranchType) {
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case a64inst_UNCONDITIONAL:
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setBits(&wrd, 26, 30, 0x5);
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setBits(&wrd, 25, 0, instr->data.BranchData.processOpData.unconditionalData.unconditionalOffset);
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break;
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case a64inst_REGISTER:
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setBits(&wrd, 16, 32, 0xD61F);
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setBits(&wrd, 5, 10, instr->data.BranchData.processOpData.registerData.src);
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break;
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case a64inst_CONDITIONAL:
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setBits(&wrd, 26, 32, 0x15);
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setBits(&wrd, 5, 24, instr->data.BranchData.processOpData.conditionalData.offset);
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setBits(&wrd, 0, 4, instr->data.BranchData.processOpData.conditionalData.cond);
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break;
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}
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return wrd;
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}
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st* firstPass(a64inst_instruction instrs[], int numInstrs) {
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// TODO:
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// -iterate over instructions, adding to symbol table
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// create symbol table and map labels to addresses/lines
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st *table = (st*)malloc(sizeof(st));
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for (int i = 0; i < numInstrs; i++) {
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// discuss defining a LABEL type
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if (instrs[i].type == a64inst_LABEL) {
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st_add(*table, &(instrs[i].data.LabelData.label), &i);
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}
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}
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return table;
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}
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word encodeDPImmediate(a64inst_instruction inst) {
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word wrd = 0;
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a64inst_DPImmediateData data = inst.data.DPImmediateData;
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setBits(&wrd, 31, 32, data.regType); // sf
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setBits(&wrd, 29, 31, data.processOp); // opc
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setBits(&wrd, 28, 29, 0x1); // constant value
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setBits(&wrd, 0, 5, data.dest); // rd
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if (data.DPIOpType == a64inst_DPI_ARITHM) {
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setBits(&wrd, 23, 26, 0x2); //opi
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setBits(&wrd, 5, 10, data.processOpData.arithmData.src); // rn
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setBits(&wrd, 22, 23, data.processOpData.arithmData.shiftImmediate); // sh
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setBits(&wrd, 10, 22, data.processOpData.arithmData.immediate); // imm12
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}
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// if wide move
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else {
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setBits(&wrd, 23, 26, 0x5); //opi
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// TODO: Check the following line, is it shiftScalar?:
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setBits(&wrd, 21, 23, data.processOpData.wideMovData.shiftScalar); // hw
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setBits(&wrd, 5, 21, data.processOpData.wideMovData.immediate); // imm16
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}
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return wrd;
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}
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word encodeDPRegister(a64inst_instruction inst) {
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word wrd = 0;
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a64inst_DPRegisterData data = inst.data.DPRegisterData;
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setBits(&wrd, 31, 32, data.regType); // sf
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setBits(&wrd, 29, 31, data.processOp); // opc
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setBits(&wrd, 28, 28, data.DPROpType); // M
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setBits(&wrd, 25 ,28, 0x5);
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setBits(&wrd, 16, 21, data.src2); // src2
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setBits(&wrd, 5, 10, data.src1); // src1
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setBits(&wrd, 0, 5, data.dest); // src2
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if (data.DPROpType == a64inst_DPR_MULTIPLY) {
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setBits(&wrd, 21, 31, 0xD8);
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setBits(&wrd, 15, 16, data.processOpData.multiplydata.negProd);
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setBits(&wrd, 10, 15, data.processOpData.multiplydata.summand);
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} else {
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// Arithmetic Logic Instruction
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setBits(&wrd, 22, 24, data.processOpData.arithmLogicData.shiftType);
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setBits(&wrd, 10, 16, data.processOpData.arithmLogicData.shiftAmount);
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if (data.processOpData.arithmLogicData.type == a64inst_DPR_ARITHM) {
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// Arithmetic
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setBits(&wrd, 24, 25, 0x1); // bit 24
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} else {
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setBits(&wrd, 21, 22, data.processOpData.arithmLogicData.negShiftedSrc2);
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}
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}
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return wrd;
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}
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word encodeSingleDataTransfer(a64inst_instruction inst) {
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word wrd = 0;
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a64inst_SingleTransferData data = inst.data.SingleTransferData;
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a64inst_SingleDataTransferData data2 = data.processOpData.singleDataTransferData;
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setBits(&wrd, 22, 32, 0x2E0);
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setBits(&wrd, 30, 31, data.regType);
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setBits(&wrd, 24, 25, data2.addressingMode == a64inst_UNSIGNED_OFFSET);
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setBits(&wrd, 22, 23, data2.transferType);
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setBits(&wrd, 5, 10, data2.base);
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setBits(&wrd, 0, 5, data.target);
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switch (data2.addressingMode) {
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// register offset
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case a64inst_REGISTER_OFFSET:
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setBits(&wrd, 21, 22, 1);
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setBits(&wrd, 10, 16, 0x1A);
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setBits(&wrd, 16, 21, data2.a64inst_addressingModeData.offsetReg);
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break;
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// unsigned offset
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case a64inst_UNSIGNED_OFFSET:
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setBits(&wrd, 10, 22, data2.a64inst_addressingModeData.unsignedOffset);
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break;
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// pre/post indexed
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default:
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setBits(&wrd, 21, 22, 0);
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setBits(&wrd, 11, 12, data2.addressingMode == a64inst_PRE_INDEXED);
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setBits(&wrd, 10, 11, 1);
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setBits(&wrd, 12, 21, data2.a64inst_addressingModeData.indexedOffset);
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break;
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}
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return wrd;
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}
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word encodeLoadLiteral(a64inst_instruction cI) {
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word wrd = 0;
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a64inst_SingleTransferData data = cI.data.SingleTransferData;
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setBits(&wrd, 24, 32, 0x18);
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setBits(&wrd, 30, 31, data.regType);
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setBits(&wrd, 5, 24, data.processOpData.loadLiteralData.offset);
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setBits(&wrd, 0, 5, data.target);
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return wrd;
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}
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word *encode(a64inst_instruction insts[], int instCount, st* table) {
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// TODO:
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// iterate over instructions again, this time replacing labels
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// with values from symbol table
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// after a line has had all the values replaced, assemble it and append
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word *arr = (word*)malloc(sizeof(word) * instCount);
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int index = 0;
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for (int i = 0; i < instCount; i++) {
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a64inst_instruction inst = insts[i];
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switch (inst.type) {
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case a64inst_DPIMMEDIATE:
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arr[index] = encodeDPImmediate(inst);
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index++;
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break;
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case a64inst_DPREGISTER:
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arr[index] = encodeDPRegister(inst);
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index++;
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break;
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case a64inst_SINGLETRANSFER:
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arr[index] = encodeSingleDataTransfer(inst);
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index++;
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break;
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case a64inst_LOADLITERAL:
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arr[index] = encodeLoadLiteral(inst);
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index++;
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break;
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case a64inst_DIRECTIVE:
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arr[index] = inst.data.DirectiveData.value;
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index++;
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break;
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case a64inst_HALT:
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arr[index] = HALT_BINARY;
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index++;
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break;
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case a64inst_LABEL:
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// Labels are handled in the first pass and used for addressing.
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break;
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case a64inst_BRANCH:
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arr[index] = encodeBranch(&inst);
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index++;
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default:
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break;
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}
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}
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return arr;
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}
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