Restructring the assembling into binary, add helper funcs
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sBubshait
parent
995c6d02fa
commit
31fa1392e1
@ -1,3 +1,4 @@
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#include <assert.h>
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#include "global.h"
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#include "a64instruction/a64instruction.h"
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#include "symboltable.c"
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@ -6,36 +7,57 @@
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#define HALT_BINARY 2315255808
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// Generates assembled code based on the two-pass assembly method
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// Temp helper function to print binary representation of a word
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// static void printBinary(word number) {
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// for (int i = 31; i >= 0; i--) {
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// putchar((number & (1 << i)) ? '1' : '0');
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// }
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// putchar('\n');
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// }
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// write the provided value to the bits in the range [lsb, msb) {inclusive, exclusive} to the word.
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// Does not modify any other bits in the word.
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void setBits(word* wrd, uint8_t lsb, uint8_t msb, word value) {
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// Ensure LSB and MSB are within range of word size, and in the correct order
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assert(lsb < msb && msb <= 32);
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// Create a mask with 1s in the range [lsb, msb) and 0s elsewhere
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word mask = 0;
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for (uint8_t i = lsb; i < msb; i++) {
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mask |= 1 << i;
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}
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// Clear the bits in the range [lsb, msb) in the word
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*wrd &= ~mask;
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// Set the bits in the range [lsb, msb) to the value
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*wrd |= (value << lsb) & mask;
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}
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// Generates assembled code based on the two-pass assembly method
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word assembleBranch(a64inst_instruction *instr) {
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word binInstr = 0;
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binInstr += (5 << 28); // 101 start of branch instr
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word wrd = 0;
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switch (instr->data.BranchData.BranchType) {
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case a64inst_UNCONDITIONAL:
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// 000101
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// 25-0: sign extended simm26
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binInstr += instr->data.BranchData.processOpData.unconditionalData.unconditionalOffset;
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setBits(&wrd, 26, 30, 0x5);
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setBits(&wrd, 25, 0, instr->data.BranchData.processOpData.unconditionalData.unconditionalOffset);
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break;
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case a64inst_REGISTER:
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// 10000
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// 11111
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// 000000
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// 9-5: address from register
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// 0000
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binInstr += ((instr->data.BranchData.processOpData.registerData.src) << 5);
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setBits(&wrd, 16, 32, 0xD61F);
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setBits(&wrd, 5, 10, instr->data.BranchData.processOpData.registerData.src);
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break;
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case a64inst_CONDITIONAL:
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// 01010100
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// 25-5: sign extended offset
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// 4-0: 0{condition}
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binInstr += ((instr->data.BranchData.processOpData.conditionalData.offset) << 5);
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binInstr += instr->data.BranchData.processOpData.conditionalData.cond;
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break;
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default:
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setBits(&wrd, 26, 32, 0x15);
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setBits(&wrd, 5, 24, instr->data.BranchData.processOpData.conditionalData.offset);
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setBits(&wrd, 0, 4, instr->data.BranchData.processOpData.conditionalData.cond);
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break;
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}
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return binInstr;
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return wrd;
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}
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st* firstPass(a64inst_instruction instrs[], int numInstrs) {
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@ -53,32 +75,30 @@ st* firstPass(a64inst_instruction instrs[], int numInstrs) {
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}
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word dpi(a64inst_instruction cI) {
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word out = 0;
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word wrd = 0;
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a64inst_DPImmediateData data = cI.data.DPImmediateData;
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// sf
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out += data.regType * (1 << 31);
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out += data.processOp * (1 << 29);
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out += 1 << 28;
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// if arithmetic
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setBits(&wrd, 31, 32, data.regType); // sf
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setBits(&wrd, 29, 31, data.processOp); // opc
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setBits(&wrd, 28, 29, 0x1); // constant value
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setBits(&wrd, 0, 5, data.dest); // rd
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if (data.DPIOpType == a64inst_DPI_ARITHM) {
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out += 1 << 24;
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// shift
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if (data.processOpData.arithmData.shiftImmediate) {
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out += 1 << 22;
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}
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out += data.processOpData.arithmData.immediate * (1 << 10);
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out += data.processOpData.arithmData.src * (1 << 5);
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setBits(&wrd, 23, 26, 0x2); //opi
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setBits(&wrd, 5, 10, data.processOpData.arithmData.src); // rn
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setBits(&wrd, 22, 23, data.processOpData.arithmData.shiftImmediate); // sh
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setBits(&wrd, 10, 22, data.processOpData.arithmData.immediate); // imm12
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}
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// if wide move
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else {
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out += 5 * (1 << 23);
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// hw
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out += data.processOpData.wideMovData.shiftScalar * (1 << 21);
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out += data.processOpData.wideMovData.immediate * (1 << 5);
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setBits(&wrd, 23, 26, 0x5); //opi
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// TODO: Check the following line, is it shiftScalar?:
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setBits(&wrd, 21, 23, data.processOpData.wideMovData.shiftScalar); // hw
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setBits(&wrd, 5, 21, data.processOpData.wideMovData.immediate); // imm16
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}
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// destination register
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out += data.dest;
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return out;
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return wrd;
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}
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word dpr(a64inst_instruction cI) {
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@ -135,49 +155,51 @@ word dpr(a64inst_instruction cI) {
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}
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word sts(a64inst_instruction cI) {
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word wrd = 0;
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a64inst_SingleTransferData data = cI.data.SingleTransferData;
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word out = 0;
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a64inst_SingleDataTransferData data2 = data.processOpData.singleDataTransferData;
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// this deals with every bit in the 31-23 range apart from sf and U
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out += (512 + 128 + 64 + 32U) * (1 << 23);
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int sf = data.regType;
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int u = 0;
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int offset = 0;
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int xn = data2.base;
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int rt = data.target;
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setBits(&wrd, 22, 32, 0x2E0);
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setBits(&wrd, 30, 31, data.regType);
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setBits(&wrd, 24, 25, data2.addressingMode == a64inst_UNSIGNED_OFFSET);
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setBits(&wrd, 22, 23, data2.transferType);
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setBits(&wrd, 5, 10, data2.base);
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setBits(&wrd, 0, 5, data.target);
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switch (data2.addressingMode) {
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// register offset
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case a64inst_REGISTER_OFFSET:
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offset += 2080 + 64 * data2.a64inst_addressingModeData.offsetReg;
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setBits(&wrd, 21, 22, 1);
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setBits(&wrd, 10, 16, 0x1A);
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setBits(&wrd, 16, 21, data2.a64inst_addressingModeData.offsetReg);
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break;
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// unsigned offset
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case a64inst_UNSIGNED_OFFSET:
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offset += data2.a64inst_addressingModeData.unsignedOffset;
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u = 1;
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setBits(&wrd, 10, 22, data2.a64inst_addressingModeData.unsignedOffset);
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break;
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// pre/post indexed
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default:
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offset = 1 + data2.addressingMode * 2 + data2.a64inst_addressingModeData.indexedOffset * 4;
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setBits(&wrd, 21, 22, 0);
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setBits(&wrd, 11, 12, data2.addressingMode == a64inst_PRE_INDEXED);
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setBits(&wrd, 10, 11, 1);
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setBits(&wrd, 12, 21, data2.a64inst_addressingModeData.indexedOffset);
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break;
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}
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out += sf * (1 << 30);
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out += u * (1 << 22);
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out += offset * 1024;
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out += xn * 32;
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out += rt;
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return out;
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return wrd;
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}
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word ldl(a64inst_instruction cI) {
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word out = 3 * (1 << 27);
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word wrd = 0;
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a64inst_SingleTransferData data = cI.data.SingleTransferData;
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int sf = data.regType;
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int simm19 = data.processOpData.loadLiteralData.offset;
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int rt = data.target;
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out += sf * (1 << 30);
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out += simm19 * 32;
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out += rt;
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return out;
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setBits(&wrd, 24, 32, 0x18);
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setBits(&wrd, 30, 31, data.regType);
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setBits(&wrd, 5, 24, data.processOpData.loadLiteralData.offset);
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setBits(&wrd, 0, 5, data.target);
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return wrd;
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}
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word *secondPass(a64inst_instruction instrs[], int numInstrs, st* table) {
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