Attempt to make code compile, fix syntax errors

src/parser.c

@@ -1,4 +1,5 @@
 #include <stdio.h>
+#include <stdlib.h>
 #include <string.h>
 #include <stdbool.h>
 #include "parser.h"

src/symboltable.c

@@ -0,0 +1,48 @@
+#include <stdio.h>
+
+typedef struct st st;
+typedef struct node node; // forward declaration
+
+typedef struct node {
+    const void* key;
+    void* value;
+    node* prev;
+    node* next;
+} node;
+
+struct st {
+    node* head;
+    node* tail;
+};
+
+// add new node to the end
+void st_add(st table, void* key, void* value) {
+    node n = {key, value, table.tail};
+    if (table.head == NULL) {
+        table.head = &n;
+        table.tail = &n;
+    }
+    else {
+        (*(table.tail)).next = &n;
+        table.tail = &n;
+    }  
+}
+
+void* nodeSearch(node* n, void* key) {
+    if (n != NULL) {
+        if ((*n).key == key) {
+            return (*n).value;
+        }
+        else {
+            return nodeSearch((*n).next, key);
+        }
+    }
+    else {
+        return NULL;
+    }
+}
+
+// returns the pointer to key of the specified node, or null, if it does not exist
+void* st_search(st table, void* key) {
+    return nodeSearch(table.head, key);
+}

src/twopassassembly.c

@@ -1,6 +1,6 @@
 #include "global.h"
 #include "a64instruction/a64instruction.h"
-#include "symboltable.h"
+#include "symboltable.c"
 //generates assembled code based on two pass assembly method
 
 
@@ -12,7 +12,7 @@ word assembleBranch(a64inst_instruction *instr){
     case a64inst_UNCONDITIONAL:
         //000101
         //25-0: sign extended simm26
-        binInstr += instr->data.processOpData.unconditionalOffset;
+        binInstr += instr->data.BranchData.processOpData.unconditionalData.unconditionalOffset;
         break;
     case a64inst_REGISTER:
         //10000
@@ -20,14 +20,14 @@ word assembleBranch(a64inst_instruction *instr){
         //000000
         //9-5: address from register
         //0000
-        binInstr += ((instr->processOpData.src)^5);
+        binInstr += ((instr->data.BranchData.processOpData.registerData.src)^5);
         break;
     case a64inst_CONDITIONAL:
         // 01010100 
         // 25-5: sign extended offset
         // 4-0: 0{condition}
-        binInstr += ((instr->processOpData.offset)^5);
+        binInstr += ((instr->data.BranchData.processOpData.conditionalData.offset)^5);
-        binInstr += instr->processOpData.cond;
+        binInstr += instr->data.BranchData.processOpData.conditionalData.cond;
         break;
     default:
         break;
@@ -49,7 +49,7 @@ st* firstPass(a64inst_instruction instrs[], int numInstrs){
     }
     return &table;
 }
-word assembleDPI(a64inst_instruction cI) {
+word dpi(a64inst_instruction cI) {
     word out = 0;
     a64inst_DPImmediateData data = cI.data.DPImmediateData;
     //sf
@@ -78,7 +78,7 @@ word assembleDPI(a64inst_instruction cI) {
     return out;
 }
 
-word assembleDPR(a64inst_instruction cI) {
+word dpr(a64inst_instruction cI) {
     word out = 0;
     a64inst_DPRegisterData data = cI.data.DPRegisterData;
     // sf
@@ -131,7 +131,7 @@ word assembleDPR(a64inst_instruction cI) {
     return out;
 }
 
-word assembleSTS(a64inst_instruction cI) {
+word sts(a64inst_instruction cI) {
     a64inst_SingleTransferData data = cI.data.SingleTransferData;
     word out = 0;
     a64inst_SingleDataTransferData data2 = data.processOpData.singleDataTransferData;
@@ -166,7 +166,7 @@ word assembleSTS(a64inst_instruction cI) {
     return out;
 }
 
-word assembleLDL(a64inst_instruction cI) {
+word ldl(a64inst_instruction cI) {
     word out = 3*(2^27);
     a64inst_SingleTransferData data = cI.data.SingleTransferData;
     int sf = data.regType;
@@ -216,7 +216,7 @@ void secondPass(a64inst_instruction instrs[], int numInstrs, st* table, word arr
                 lbl++;
                 break;
             case a64inst_BRANCH:
-                arr[index] = assembleBranch(&cI, table, lbl);
+                arr[index] = assembleBranch(&cI);
                 index++;
             default:
                 break;