Merge remote-tracking branch 'origin/assembler' into Assembler-G
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commit
07ff159c9b
28
src/a64instruction.h
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28
src/a64instruction.h
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#ifndef __A64INSTRUCTION__
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#define __A64INSTRUCTION__
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#include "a64instruction_DPImmediate.h"
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#include "a64instruction_Branch.h"
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#include "a64instruction_SingleTransfer.h"
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// Define the types of instructions in subset of the AArch64 Instruction Set implemented.
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// Each type is defined by the format of the instruction's operand(s).
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typedef enum {
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a64inst_DPIMMEDIATE,
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a64inst_DPREGISTER,
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a64inst_SINGLETRANSFER,
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a64inst_LOADLITERAL,
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a64inst_BRANCH,
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a64inst_HALT
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} a64inst_type;
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// Structure the holds the type and operand data of an instruction
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typedef struct {
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a64inst_type type;
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union {
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a64inst_DPImmediateData DPImmediateData;
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a64inst_BranchData BranchData;
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a64inst_SingleTransferData SingleTransferData;
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} data;
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} a64inst_instruction;
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#endif
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41
src/a64instruction_Branch.h
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41
src/a64instruction_Branch.h
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#include <stdbool.h>
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#include "a64instruction_global.h"
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#include "global.h"
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typedef enum {
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a64inst_UNCONDITIONAL = 0,
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a64inst_REGISTER = 1,
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a64inst_CONDITIONAL = 2
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} a64inst_BranchType;
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typedef struct {
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word unconditionalOffset;
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} a64inst_Branch_UnconditionalData;
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typedef struct {
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a64inst_regSpecifier src;
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} a64inst_Branch_RegisterData;
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typedef enum {
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EQ = 0, // Equal
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NE = 1, // Not Equal
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GE = 10, // Signed greater or equal
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LT = 11, // Signed less than
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GT = 12, // Signed greater than
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LE = 13, // signed less than or equal
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AL = 14 // Always
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} a64inst_ConditionType; //a64inst_Branch_ConditionType?
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typedef struct {
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a64inst_ConditionType cond;
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word offset;
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} a64inst_Branch_ConditionalData;
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typedef struct {
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a64inst_BranchType BranchType;
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union {
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a64inst_Branch_UnconditionalData unconditionalData;
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a64inst_Branch_RegisterData registerData;
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a64inst_Branch_ConditionalData conditionalData;
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} processOpData;
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} a64inst_BranchData;
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7
src/a64instruction_DP.h
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7
src/a64instruction_DP.h
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// Denotes the type of arithmetic operations supported by the architecture
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typedef enum {
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a64inst_ADD = 0,
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a64inst_ADDS = 1,
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a64inst_SUB = 2,
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a64inst_SUBS = 3
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} a64inst_arithmOp;
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42
src/a64instruction_DPImmediate.h
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42
src/a64instruction_DPImmediate.h
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#include <stdbool.h>
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#include "a64instruction_global.h"
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#include "a64instruction_DP.h"
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// Denotes the type of data processing operation
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typedef enum {
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a64inst_DPI_ARITHM,
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a64inst_DPI_WIDEMOV
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} a64inst_DPIOpType;
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// Denotes the type of wide move operations supported by the architecture
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typedef enum {
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a64inst_MOVN = 0,
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a64inst_UNDEFINED = 1,
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a64inst_MOVZ = 2,
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a64inst_MOVK = 3
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} a64inst_wideMovOp;
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// Holds data specific to arithmetic immediate data processing instructions
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typedef struct {
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bool shiftImmediate;
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uint16_t immediate;
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a64inst_regSpecifier src;
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} a64inst_DPImmediate_ArithmData;
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// Holds data specific to wide move immediate data processing instructions
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typedef struct {
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uint8_t shiftScalar;
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uint16_t immediate;
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} a64inst_DPImmediate_WideMovData;
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// Holds data for immediate data processing instructions
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typedef struct {
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a64inst_regType regType;
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a64inst_DPIOpType DPIOpType;
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unsigned int processOp;
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union {
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a64inst_DPImmediate_ArithmData arithmData;
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a64inst_DPImmediate_WideMovData wideMovData;
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} processOpData;
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a64inst_regSpecifier dest;
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} a64inst_DPImmediateData;
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58
src/a64instruction_DPRegister.h
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58
src/a64instruction_DPRegister.h
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#include <stdbool.h>
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#include "a64instruction_global.h"
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#include "a64instruction_DP.h"
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// Denotes the type of data processing operation
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typedef enum {
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a64inst_DPR_ARITHMLOGIC,
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a64inst_DPR_MULTIPLY
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} a64inst_DPROpType;
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// Denotes the logical operations supported by the architecture
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typedef enum {
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a64inst_AND = 0,
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a64inst_OR = 1,
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a64inst_XOR = 2,
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a64inst_AND_FLAGGED = 3
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} a64inst_logicOp;
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// Denotes the different kinds of shifts supported by the architecture
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typedef enum {
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a64inst_LSL = 0,
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a64inst_LSR = 1,
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a64inst_ASR = 2,
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a64inst_ROR = 3
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} a64inst_ShiftType;
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// Holds data specific to arithmetic/logic register data processing instructions
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typedef struct {
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enum {
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a64inst_DPR_ARITHM = 0,
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a64inst_DPR_LOGIC = 1
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} type;
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a64inst_ShiftType shiftType;
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bool negShiftedSrc2; // Guaranteed to be 0 for arithmetic instructions
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} a64inst_DPRegister_ArithmLogicData;
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// Holds data specific to multiply register data processing instructions
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typedef struct {
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bool negProd;
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a64inst_regSpecifier summand;
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} a64inst_DPRegister_MultiplyData;
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// Holds data for register data processing instructions
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typedef struct {
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a64inst_regType regType;
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a64inst_DPROpType DPROpType;
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union {
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a64inst_logicOp logicOp;
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a64inst_arithmOp arithmOp;
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} processOpId;
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a64inst_regSpecifier src2;
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union {
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a64inst_DPRegister_ArithmLogicData arithmLogicData;
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a64inst_DPRegister_MultiplyData multiplydata;
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} processOpData;
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a64inst_regSpecifier src1;
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a64inst_regSpecifier dest;
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} a64inst_DPRegisterData;
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47
src/a64instruction_SingleTransfer.h
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47
src/a64instruction_SingleTransfer.h
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#include <stdbool.h>
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#include "a64instruction_global.h"
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#include "global.h"
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typedef enum {
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a64inst_SINGLE_TRANSFER_SINGLE_DATA_TRANSFER = 1,
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a64inst_SINGLE_TRANSFER_LOAD_LITERAL = 0
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} a64inst_SingleTransferType;
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typedef enum {
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a64inst_STORE,
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a64inst_LOAD
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} a64inst_TransferType;
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typedef enum {
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a64inst_REGISTER_OFFSET = 2,
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a64inst_PRE_INDEXED = 1,
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a64inst_POST_INDEXED = 0,
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a64inst_UNSIGNED_OFFSET = 3
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} a64inst_AddressingMode;
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typedef struct {
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a64inst_TransferType transferType;
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a64inst_AddressingMode addressingMode;
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union {
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a64inst_regSpecifier offsetReg;
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uint16_t indexedOffset;
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uint16_t unsignedOffset;
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} a64inst_addressingModeData;
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a64inst_regSpecifier base;
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} a64inst_SingleDataTransferData;
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typedef struct {
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uint32_t offset;
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} a64inst_LoadLiteralData;
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typedef struct {
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a64inst_SingleTransferType SingleTransferOpType;
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a64inst_regType regType;
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a64inst_regSpecifier target;
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union {
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a64inst_SingleDataTransferData singleDataTransferData;
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a64inst_LoadLiteralData loadLiteralData;
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} processOpData;
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} a64inst_SingleTransferData;
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14
src/a64instruction_global.h
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14
src/a64instruction_global.h
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#ifndef __A64INSTRUCTION_GLOBAL__
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#define __A64INSTRUCTION_GLOBAL__
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#include <stdint.h>
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// Specifies the register being referred to
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typedef uint8_t a64inst_regSpecifier;
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// Denotes the type of register being referred to
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typedef enum {
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a64inst_W = 0,
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a64inst_R = 1
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} a64inst_regType;
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#endif
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62
src/fileio.c
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62
src/fileio.c
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#include <stdio.h>
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#include <string.h>
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//validates inputted charlist as valid filename against expected extension
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int isValidFileFormat(char filename[], char expectedExtension[]){
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int *pointLoc = strrchr(filename, '.');
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if(pointLoc != NULL){
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if(strcmp(pointLoc, expectedExtension)==0){
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return(1);
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}
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}
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return(0);
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}
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//writes a list of words (list of binary instructions) to a named output file
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int writeBinaryFile(word instrs[], char outputFile[]){
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if (!isValidFileFormat(filename, "bin")){
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exit(EXIT_FAILURE);
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}
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FILE *fp;
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fp = fopen(outputFile, "wb");
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if(fp == NULL){
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exit(EXIT_FAILURE);
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}
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fwrite(instrs, sizeof(word), sizeof(instrs), fp);
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fclose(fp);
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exit(EXIT_SUCCESS);
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}
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//reads assembly file of "inputFile" name, and passes
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//each line into a parser
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//TODO: allocate whole file in memory, line-by-line
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int readAssemblyFile(char inputFile[]) {
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if (!isValidFileFormat(filename, "s")){
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exit(EXIT_FAILURE);
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}
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FILE *fp;
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char savedLine[sizeof(a64inst_instruction)];
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fp = fopen(inputFile, "r");
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if(fp == NULL){
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exit(EXIT_FAILURE);
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}
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while (fgets(savedLine, MAX_ASM_LINE_LENGTH-1, fp) != NULL) {
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// removes newline char before saving them
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savedLine[strcspn(savedLine, "\n")] = 0;
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}
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exit(EXIT_SUCCESS);
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}
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63
src/parser.c
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63
src/parser.c
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#include <stdio.h>
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#include <string.h>
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#include "parser.h"
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#include "a64instruction.h"
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//takes input string, read from asm file and returns
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//input as an a64 instruction
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//TODO:
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// - use string matching to get opcode, and operands (DONE)
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// - check operand count (DONE)
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// - match opcode to a64 struct types
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// - count operands and match type/values
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// - generate final a64inst and return
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//takes string of operands, and reference to operandcounter
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//takes input of result array
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//outputs array of operands
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void tokeniseOperands(char* str, int operandCount, char *operands[]){
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char *operandsDupe = strdup(str);
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int operandCount = 0;
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char *operand = strtok(operandsDupe, OPERAND_DELIMITER);
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operands[0] = operand;
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while (operand != NULL){
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operandCount++;
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operand = strtok(NULL, OPERAND_DELIMITER);
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operands[operandCount] = operand;
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}
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}
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//takes inputted assembly line and returns a
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//pointer to an abstract representation of the instruction
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a64inst_instruction *parser(char asmLine[]){
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a64inst_instruction *instr = malloc(sizeof(a64inst_instruction));
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if (instr == NULL){
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exit(EXIT_FAILURE);
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}
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//"opcode operand1, {operand2}, ..."
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//duplicated as strtok modifies the input string
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char *stringptr = strdup(asmLine);
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char *opcode = strtok(stringptr, " ");
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char *operands = strtok(NULL, "");
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if(opcode[0]=="."){
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//type is directive
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} else if(opcode[strlen(opcode)-1]==":") {
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//type is label
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} else {
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//type is instruction
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int operandCount = 0;
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const char *operandList[4];
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tokeniseOperands(operands, &operandCount, operandList);
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}
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return(a64inst_instruction);
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}
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1
src/parser.h
Normal file
1
src/parser.h
Normal file
@ -0,0 +1 @@
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#define OPERAND_DELIMITER ", "
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