Add decode for DP immediate instructions w/ S#
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@ -33,10 +33,7 @@ typedef struct {
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typedef struct {
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typedef struct {
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a64inst_regType regType;
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a64inst_regType regType;
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a64inst_DPIOpType DPIOpType;
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a64inst_DPIOpType DPIOpType;
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union {
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unsigned int processOp;
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a64inst_arithmOp arithmOp;
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a64inst_wideMovOp movOp;
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} processOpId;
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union {
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union {
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a64inst_DPImmediate_ArithmData arithmData;
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a64inst_DPImmediate_ArithmData arithmData;
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a64inst_DPImmediate_WideMovData wideMovData;
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a64inst_DPImmediate_WideMovData wideMovData;
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46
src/decode.c
46
src/decode.c
@ -8,12 +8,14 @@
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static word getBits(word wrd, uint8_t lsb, uint8_t msb) {
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static word getBits(word wrd, uint8_t lsb, uint8_t msb) {
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// Ensure LSB and MSB are within range of word size, and in the correct order
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// Ensure LSB and MSB are within range of word size, and in the correct order
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assert(lsb < msb && msb < BYTE_BITS);
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assert(lsb < msb && msb <= WORD_BITS);
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wrd &= (1 << msb) - 1;
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wrd &= (1 << msb) - 1;
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return wrd >> lsb;
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return wrd >> lsb;
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}
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}
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// Given a binary word, return its internal representation as an a64instruction struct encoding the same
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// information.
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a64inst_instruction *decode(word wrd) {
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a64inst_instruction *decode(word wrd) {
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a64inst_instruction *inst = malloc(sizeof(a64inst_instruction));
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a64inst_instruction *inst = malloc(sizeof(a64inst_instruction));
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@ -22,14 +24,40 @@ a64inst_instruction *decode(word wrd) {
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exit(1);
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exit(1);
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}
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}
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word DPImmFlag = getBits(wrd, BRANCH_CONDITIONAL_COND_LSB, BRANCH_CONDITIONAL_COND_MSB);
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word typeId = getBits(wrd, TYPE_ID_LSB, TYPE_ID_MSB);
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// Halt interpretation
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if (wrd == HALT_WORD) {
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if (wrd == HALT_WORD) {
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inst->type = a64inst_HALT;
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inst->type = a64inst_HALT;
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} else if (DPImmFlag == 0) {
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inst->type = a64inst_DPIMMEDIATE;
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}else if (DPImmFlag == 1) {
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// Data Processing Immediate interpretation
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} else if (typeId == DP_IMM_ID) {
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inst->type = a64inst_DPIMMEDIATE;
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inst->data.DPImmediateData.regType = getBits(wrd, DP_IMM_WIDTH_LSB, DP_IMM_WIDTH_MSB);
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inst->data.DPImmediateData.processOp = getBits(wrd, DP_IMM_OP_LSB, DP_IMM_OP_MSB);
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inst->data.DPImmediateData.dest = getBits(wrd, DP_IMM_DEST_LSB, DP_IMM_DEST_MSB);
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switch(getBits(wrd, DP_IMM_OPTYPE_LSB, DP_IMM_OPTYPE_MSB)) {
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case DP_IMM_OPTYPE_ARITHM:
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inst->data.DPImmediateData.DPIOpType = a64inst_DPI_ARITHM;
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inst->data.DPImmediateData.processOpData.arithmData.shiftImmediate = getBits(wrd, DP_IMM_ARITHM_SHIFTFLAG_LSB, DP_IMM_ARITHM_SHIFTFLAG_MSB);
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inst->data.DPImmediateData.processOpData.arithmData.immediate = getBits(wrd, DP_IMM_ARITHM_IMMVAL_LSB, DP_IMM_ARITHM_IMMVAL_MSB);
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inst->data.DPImmediateData.processOpData.arithmData.src = getBits(wrd, DP_IMM_ARITHM_DEST_LSB, DP_IMM_ARITHM_DEST_MSB);
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break;
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case DP_IMM_OPTYPE_WIDEMOV:
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inst->data.DPImmediateData.DPIOpType = a64inst_DPI_WIDEMOV;
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inst->data.DPImmediateData.processOpData.wideMovData.shiftScalar = getBits(wrd, DP_IMM_WIDEMOV_SHIFTSCALAR_LSB, DP_IMM_WIDEMOV_SHIFTSCALAR_MSB);
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inst->data.DPImmediateData.processOpData.wideMovData.immediate = getBits(wrd, DP_IMM_WIDEMOV_IMMVAL_LSB, DP_IMM_WIDEMOV_IMMVAL_MSB);
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break;
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default:
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fprintf(stderr, "Unknown immediate data processing operation type found!\n");
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exit(1);
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break;
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}
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} else if (typeId == BRANCH_ID) {
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inst->type = a64inst_BRANCH;
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inst->type = a64inst_BRANCH;
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word branchTypeFlag = getBits(wrd, BRANCH_TYPE_LSB, BRANCH_TYPE_MSB);
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word branchTypeFlag = getBits(wrd, BRANCH_TYPE_LSB, BRANCH_TYPE_MSB);
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@ -48,7 +76,7 @@ a64inst_instruction *decode(word wrd) {
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if(conditionFlag <= 1 || (conditionFlag >= 10 && conditionFlag <= 14)) {
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if(conditionFlag <= 1 || (conditionFlag >= 10 && conditionFlag <= 14)) {
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inst->data.BranchData.processOpData.conditionalData.cond = conditionFlag;
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inst->data.BranchData.processOpData.conditionalData.cond = conditionFlag;
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} else {
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} else {
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fprintf(stderr, "Error: Unknown condition detected.\n");
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fprintf(stderr, "Unknown condition detected!\n");
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exit(1);
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exit(1);
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}
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}
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@ -64,12 +92,12 @@ a64inst_instruction *decode(word wrd) {
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break;
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break;
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}
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}
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} else if (getBits(wrd, DATA_PROCESSING_REG_LSB, DATA_PROCESSING_REG_MSB) == 1) {
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} else if (getBits(wrd, DP_REG_LSB, DP_REG_MSB) == 1) {
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inst->type = a64inst_DPREGISTER;
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inst->type = a64inst_DPREGISTER;
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} else {
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} else {
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// Load and Store, or unknown
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// Load and Store, or unknown
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}
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}
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return inst;
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}
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}
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33
src/decode.h
33
src/decode.h
@ -1,14 +1,37 @@
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#include "global.h"
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#include "global.h"
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#include "a64instruction.h"
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#include "a64instruction.h"
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#define BYTE_BITS 8
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#define WORD_BITS 32
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#define HALT_WORD 0x8a000000
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#define HALT_WORD 0x8a000000
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#define DATA_PROCESSING_IMM_LSB 26
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#define TYPE_ID_LSB 26
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#define DATA_PROCESSING_IMM_MSB 29
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#define TYPE_ID_MSB 29
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#define DP_IMM_ID 4
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#define BRANCH_ID 5
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#define DATA_PROCESSING_REG_LSB 25
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#define DP_REG_LSB 25
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#define DATA_PROCESSING_REG_MSB 26
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#define DP_REG_MSB 26
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#define DP_IMM_WIDTH_LSB 31
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#define DP_IMM_WIDTH_MSB 32
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#define DP_IMM_OP_LSB 29
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#define DP_IMM_OP_MSB 31
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#define DP_IMM_DEST_LSB 0
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#define DP_IMM_DEST_MSB 5
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#define DP_IMM_OPTYPE_LSB 23
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#define DP_IMM_OPTYPE_MSB 26
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#define DP_IMM_OPTYPE_ARITHM 2
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#define DP_IMM_OPTYPE_WIDEMOV 5
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#define DP_IMM_ARITHM_SHIFTFLAG_LSB 22
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#define DP_IMM_ARITHM_SHIFTFLAG_MSB 23
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#define DP_IMM_ARITHM_IMMVAL_LSB 10
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#define DP_IMM_ARITHM_IMMVAL_MSB 22
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#define DP_IMM_ARITHM_DEST_LSB 5
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#define DP_IMM_ARITHM_DEST_MSB 10
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#define DP_IMM_WIDEMOV_SHIFTSCALAR_LSB 21
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#define DP_IMM_WIDEMOV_SHIFTSCALAR_MSB 23
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#define DP_IMM_WIDEMOV_IMMVAL_LSB 5
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#define DP_IMM_WIDEMOV_IMMVAL_MSB 21
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#define BRANCH_TYPE_LSB 30
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#define BRANCH_TYPE_LSB 30
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#define BRANCH_TYPE_MSB 32
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#define BRANCH_TYPE_MSB 32
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